This is my attempt to make a simple digital logic circuit using FPGA. So I have used DE0-nano FPGA Kit and 7-segment LED display lying idle in my collection. I have used standard libraries than building my own counter and 7-segment decoder circuit.
The design comprises of two major units. One is Divide-by-n counter and another one is BCD-To-Seven-Segment Decoder. The counter unit counts the pulses generated by a push button in the kit. The 4-bit counter output is given to 7-segment decoder to convert the same to corresponding 7-segment output.
The following schematic drawn in Quartus Workspace shows the complete design. 7490 is the Divide-by-n Counter and 7448 is BCD-To-Seven-Segment Decoder. These can be inserted in your design by File -> New… -> Block/Schematic Diagram -> Symbol Tool (AND gate icon) -> Libraries -> Others -> maxplus2 -> 7490/7448.
Configure 7490 as Divide-by-10-counter by connection QA with CLKB. Push button KEY0 in kit is configured to connect to CLKA. 7 segment output OA to OG are connected to GPIO0 header pins.
Note: You will see PIN assignments shown in below diagram only after doing Pin assignments following in this article.
All seven outputs of decoder are connected to 7-segment common cathode LED display through 1K resistor. DE0-nano’s Gnd is connected to LED display’s ground.
The Pin assignment to be done by following Assignments -> Pin Planner. Ensure that I/O Standard is 3.3V LVTTL.
You may download the Quartus project Workspace for this project here: binary_counter.zip
Counter in action
Here is the counter in live action