Basic SOPC, BSP and Application development with DE0-nano Altera FPGA Kit

Altera FPGA DE0-nano kit has Cyclone IV E series FPGA with 32MB SDRAM, 40 Pin GPIOs, Accelerometer, AD Converters, built-in LEDs and Switches, etc. necessary to explore the world of FPGA. Altera gives excellent free development tools along with this kit to develop a complete solution right from designing a SOPC based on NIOS-II soft core processor to auto-generated BSP for the same through a simple Eclipse based tool and application development on top of it. There are many number of guides available online to explain the step by step procedure to develop a SOPC and C application for the same. So I skip this step by step process here instead summarizes the design and application code. This is going to be base for follow-up articles related to this project. Following this I will be writing more articles on internal design of SOPC and structure of BSP like very low level code crt0.S – C Run time environment initialization and BSP library, etc.

Here is official step by step guide to develop a complete solution from Altera:

1. Download PDF guide from official Altera web site.

2. Copy of this official guide hosted in this site can be downloaded here: Introduction_to_the_Altera_SOPC_Builder

Architecture of SOPC

DE0 Nano Board
DE0 Nano Board

The objective of this project is to use two built-in push switches in DE0 Nano board for input and 8 LEDs as output devices. We would like get Interrupt when any of these switches are pressed, Interrupt Service Routine in main C Application should process this and use LED to notify that it is processed. The following architecture diagram shows this (courtesy: Altera – diagram slightly modified for this project)

Nios-II Basic SOPC Diagram

SOPC Design

 

Project Settings
Project Settings

The above System configuration is for DE0 Nano board. Create System Components design as shown below. Ensure that PIO Switches IRQ Line is connected to CPU.

System Contents
System Contents
Address Map
Address Map

 

The following figures shows various components and its configuration.

Clock Frequency is set as 50MHz in this DE0 Nano case.

Clock Source
Clock Source

NIOS II Processor component is configured as Nios II/e core which is a basic Core. Ensure that On Chip Memory is configured to host Exception Vector. Reset Vector Offset and Reset vector to be configured as 0x00000000 and 0x00004000 respectively.

Nios II Processor Configuration
Nios II Processor Configuration

JTAG Debug Module for NIOS II is configured at Level 1 as shown below.

Nios II Processor JTAG Configuration
Nios II Processor JTAG Configuration

On Chip Memory is configured for the size of 16KB and Data width of 32 bits. Here ECC is disabled as it is a simple SOPC. Ensure that “Initialize memory content” option selected. During initial configuration the “Enable non-default initialization file” can be left out without selecting. Once your C Application is built, you can very well come back to this configuration page to enable this and select your generated application HEX file as memory initialization file.

On-Chip Memory (RAM or ROM)
On-Chip Memory (RAM or ROM)

Two push switches are configured as input. So width is configured as 2 and direction as Input while configuring PIO Input Switches. Enable “Synchronously capture” and Edge Type as “RISING”. Enable “Generate IRQ” and type as “EDGE”. You need to hard wire PIO inputs 0x00000000.

PIO (Parallel I-O) - pio_switches
PIO (Parallel I-O) – pio_switches

8 LEDs are used as output devices, so enabled Data width of 8 in PIO Output component configuration. Set direction as Output and Reset value as 0x00000000. If you want individual bit set/clear macros, enable it.

PIO (Parallel I-O) - pio_led
PIO (Parallel I-O) – pio_led

To assign a unique System ID you need to enter any 32 bit hexadecimal value.

System ID Peripheral
System ID Peripheral

Generated Design Output

After generating design through QSys, your final design should look like below shown interconnect diagrams. You can view these from “System” -> “Show System With QSys Interconnect”.

Detailed System Contents
Detailed System Contents
Memory Mapped Interconnect
Memory Mapped Interconnect

Chip Planning

While doing Chip Planning the below figure shows how it looks like in case DE0 Nano. It varies depending on board which you use. Please refer user guide of the board to know which pins the Clock, LED and Switches are connected to and follow the same.

Chip Planner
Chip Planner

Board Support Package (BSP) Settings

BSP Main Settings
BSP Main Settings

The above figure shows the basic settings BSP requires. Ensure that only those 4 settings in right pane are checked in to get smaller and optimized code.

Once BSP is built you can see following configuration.

BSP Drivers
BSP Drivers
BSP Linker Sections
BSP Linker Sections

The following figure shows files copied from installation and files generated while building this BSP.

BSP File Generation
BSP File Generation

Main Application

Here is the main application which handles Interrupt from Switches and Turn On LEDs patterns according to that.

/*
 * main.c
 *
 *  Created on: July 15, 2015
 *      Author: KaruppuSwamy
 */

#include "system.h"
#include "sys/alt_irq.h"
#include "altera_avalon_pio_regs.h"

extern int alt_irq_register (alt_u32 id, void* context, alt_isr_func handler);

void switch_isr(void *isr_context)
{
	long i;
	// Turn on odd bit LEDs
	IOWR_ALTERA_AVALON_PIO_DATA(PIO_LED_BASE, 0xAA);
	for (i=0; i < 999999; i++);
	// Turn on even bit LEDs
	IOWR_ALTERA_AVALON_PIO_DATA(PIO_LED_BASE, 0x55);

	// lsb 0/1 (switch-0/1) are again enabled for interrupt
	IOWR_ALTERA_AVALON_PIO_IRQ_MASK(PIO_SWITCHES_BASE, 0x03);
	// Reset Edge capture register of Switches 
	IOWR_ALTERA_AVALON_PIO_EDGE_CAP(PIO_SWITCHES_BASE, 0x00);
}

void err_loop()
{
	// Turn on all LEDs to notify error
	IOWR_ALTERA_AVALON_PIO_DATA(PIO_LED_BASE, 0xff);
}

int main()
{
	// Initialize all LEDs to turn OFF
	IOWR_ALTERA_AVALON_PIO_DATA(PIO_LED_BASE, 0x00);

	// lsb 0/1 (switch-0/1) are enabled for interrupt
	IOWR_ALTERA_AVALON_PIO_IRQ_MASK(PIO_SWITCHES_BASE, 0x03);
	// Reset Edge capture register of Switches
	IOWR_ALTERA_AVALON_PIO_EDGE_CAP(PIO_SWITCHES_BASE, 0x00);

	// If Switches ISR register/enable failed; err_loop() doesn't return
	if (alt_irq_register(PIO_SWITCHES_IRQ, 0, switch_isr))
		err_loop();

	while (1);
}

 

Download the project here first_sopc.zip.

Here is the SOPC in action:

The next post will narrate on what really happens when you reset the FPGA board before your C main function starts. This is very interesting are where we will be learning on C Run time environment code which runs at reset vector of NIOS II processor.

 

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